Method of fabricating a wide-based box- structured capacitor containing hemi-spherical grains

ABSTRACT

A method of fabricating a wide-based boxed-structured capacitor containing hemi-spherical silicon grains. A substrate is provided with a source/drain and a first dielectric layer is formed on the substrate with a node contact opening. Then a doped polysilicon layer and a doped amorphous silicon layer are formed sequentially on the first dielectric layer. An etching step is performed to etch the doped amorphous silicon layer and the doped polysilicon layer and a wide-based lower electrode is formed by adjusting flow speeds of chlorine and of hydrogen bromide. Hemi-spherical silicon grains are formed on the surface of the doped amorphous silicon layer in the lower electrode. A second dielectric layer and an upper electrode are formed sequentially on the lower electrode and the capacitor is completed.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the priority benefit of Taiwanapplication serial no. 89103946, filed Mar. 6, 2000.

BACKGROUND OF THE INVENTION

[0002] 1. Field of Invention

[0003] The present invention relates to a method of fabricating asemiconductor memory capacitor. More particularly, the present inventionrelates to a method of fabricating a wide-based box-structured capacitorcontaining hemi-spherical grains.

[0004] 2. Description of Related Art

[0005] When semiconductor manufacture moves into the deep sub-micronprocess, the device size becomes smaller and the available space forcapacitors decreases. In contrast, as the application software increasesin size, the required storage capacity of the capacitor needs to belarger. Consequently, the method for fabricating the capacitor in adynamic random access memory (DRAM) device has to be changed, in orderto be compatible with the market requirement for smaller device size andlarger memory size.

[0006] The capacitor is the heart for storing information in the DRAMdevice. As long as the capacitor stores more charges, less damaginginfluences are induced by noise, for example, soft errors, which arecaused by α particles, can be greatly reduced during informationreading; furthermore, the frequency for refresh can be reduced as well.

[0007] The storage capacity of the conventional DRAM device is smallbecause a two-dimensional capacitor, that is, a planar type capacitor,is used in the integrated circuit manufacture process. The planar typecapacitor takes quite large areas of a semiconductor substrate to storecharges; therefore, it is not suitable for the design ofhigh-integration devices. Three-dimensional capacitors are used forhigh-integration DRAM devices.

[0008] However, simple structures of three-dimensional capacitorsnowadays can no longer satisfy the need for the memory device of higherintegration. Therefore, methods for increasing surface areas of DRAMcapacitors within small available spaces for capacitors have beendeveloped. Variant structures have been used for capacitors to increasethe storage capacity of the memory device, such as stacked types andtrench types. Stacked type structures includes double-stacked type,fin-structured type, cylindrical type, spread-stacked type andbox-structured type structures.

[0009] It is an important task for capacitors to maintain enough storagecapacity in processes of semiconductor manufacture below 0.25 μm. Oneway of increasing the storage capacity for capacitors is to increase thesurface areas of capacitors. Taking crown-structured capacitors forexample, hemi-spherical grains (HSG) are formed on the surfaces of lowerelectrodes of the crown-structured capacitors to increase the storagecapacity of capacitors in processes of semiconductor manufacture below0.18 μm.

[0010]FIG. 1A to FIG. 1C are schematic, cross-sectional viewsillustrating the process steps of fabricating a lower electrode of abox-structured DRAM capacitor according to the prior art. Referring toFIG. 1A, source/drains 102 are formed in a substrate 100. A siliconoxide layer 104 is deposited on substrate 100, and then node contactopenings 106 are formed by photolithography and etching. A dopedamorphous silicon layer 110 is deposited on substrate 100 and insideopenings 106 by low-pressure chemical vapor deposition (LPCVD) at about530 degrees Centigrade.

[0011] Referring to FIG. 1B, amorphous silicon layer 110 is defined toform lower electrodes 110 a.

[0012] Referring to Fig. 1C, hemi-spherical silicon grains (HSG-Si) 112are grown on the surfaces of lower electrodes 110 a, and lowerelectrodes 110 b with larger surface areas are formed thereon. Becauseof the requirement for high integration, the areas for formingcapacitors are limited. Within these available areas, if a distance 114between two adjacent electrodes is too short, hemi-spherical silicongrains 112 on the surfaces of adjacent electrodes 110 b contact eachother and induce short circuits. On the contrary, if distance 114 is toolong, then lower electrodes 110 b fall down due to overly thin bases.

SUMMARY OF THE INVENTION

[0013] The invention provides a method of fabricating a wide-basedbox-structured capacitor containing hemi-spherical grains, so that thelower electrodes are not so thin that they fall down. Furthermore, itincreases integration for capacitors but cause no more short circuitsproblems

[0014] As embodied and broadly described herein, a substrate is providedwith a source/drain and a first dielectric layer is formed on thesubstrate with a node contact opening that exposes the source/drain.Then a doped polysilicon layer and a doped amorphous silicon layer areformed sequentially on the first dielectric layer. A first etching stepis performed to etch the doped amorphous silicon layer and the dopedpolysilicon layer until the first dielectric layer is exposed and alower electrode is formed thereon in the node contact opening and on thesurrounding first dielectric layer. The first etching step comprises theusage of a first flow speed for chlorine and a second flow speed forhydrogen bromide. A second etching step is performed on the lowerelectrode with a third flow speed of chlorine and a fourth flow speed ofhydrogen bromide. The first flow speed is higher than the third flowspeed and the second flow speed is lower than the fourth flow speed. Awide-based lower electrode is formed by adjusting flow speeds ofchlorine and of hydrogen bromide and duration of the second etchingstep. Hemi-spherical silicon grains are formed on the surface of thedoped amorphous silicon layer in the lower electrode. A seconddielectric layer and an upper electrode are formed sequentially on thelower electrode and the capacitor is completed.

[0015] As embodied and broadly described herein, hemi-spherical silicongrains only can grow on the surface of the doped amorphous siliconlayer, but not on the surface of the doped polysilicon layer that isformed before the formation of the doped amorphous silicon layer.Therefore, the growth of hemi-spherical silicon grains does not causebridging between adjacent lower electrodes, nor induce short circuits inthe capacitors. Moreover, the bases of the lower electrodes are widerthan the tops of the lower electrodes, so that the lower electrodes donot easily fall down.

[0016] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary, andare intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention. In the drawings,

[0018]FIG. 1A to FIG. 1C are schematic, cross-sectional viewsillustrating the process steps of fabricating a lower electrode of abox-structured DRAM capacitor according to the prior art; and

[0019]FIG. 2A to FIG. 2C are schematic, cross-sectional viewsillustrating the process steps of fabricating a lower electrode of awide-based box-structured capacitor according to one preferredembodiment of this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Referring to FIG. 2A, source/drains 202 are formed by, forexample, ion implantation, in a substrate 200. A dielectric layer 204 isthen formed on substrate 200. A material of dielectric layer 204 can be,for example, silicon oxide, formed by, for example, low pressurechemical vapor deposition while using Si(OC₂H₅)₄ as a gas source. Nodecontact openings 206 are formed in dielectric layer 204 by processesthat comprise photolithography and etching.

[0021] A doped polysilicon layer 212 is deposited by, for example,chemical vapor deposition, over dielectric layer 204 and node contactopenings 206. Dopants for doped polysilicon layer 212 can be doped, forexample, during deposition, in an in situ doping process, or by ionimplantation after deposition. A doped amorphous silicon layer 210 isformed by, for example, low pressure chemical vapor deposition, on dopedpolysilicon layer 212.

[0022] Referring to FIG. 2B, a first etching step is performed to removepart of doped amorphous silicon layer 210 and part of doped polysiliconlayer 212, which is above dielectric layer 204, resulting in dopedamorphous silicon layer 210 a and doped polysilicon layer 212 a. Lowerelectrodes 224 a are formed thereon with the bases wider than the tops.A second etching step is then performed to prevent bridging betweenadjacent lower electrodes 224 a because the adjacent distances are tooshort.

[0023] The first etching step and the second etching step can beachieved by, for example, adjusting flow speeds of chlorine and hydrogenbromide in reactive ion etching to obtain inclines for lower electrodes224 a, so that the bases are wider than the tops in lower electrodes 224a.

[0024] In general, the degree of slope for inclines in lower electrodes224 a increases as the flow speed of hydrogen bromide increases. It isbecause the ions produced by hydrogen bromide react with the siliconfrom doped amorphous silicon layer 210 a and doped polysilicon layer 212a to form SiBr_(x)H_(y), and SiBr_(x)H_(y) is deposited on the inclinesof lower electrodes 224 a and decreases etching rates for the inclines.Additionally, as a flow volume of chlorine increases, or etchingduration for the second etching step is extended, the degree of slopefor inclines in lower electrodes 224 a decreases, which means lowerelectrodes 224 a are more vertical.

[0025] Preferable operation conditions for the first etching stepcomprise a pressure range for the reaction chamber of about 12 to about18 militorrs, a power range for the RF source of about 400 to about 500Watts, a flow speed for chlorine of about 60 to about 80 sccm (standardcubic centimeter per minute), and a flow speed for hydrogen bromide ofabout 100 to about 150 sccm. Preferable operation conditions for thesecond etching step comprise a pressure range for the reaction chamberof about 35 to about 45 militorrs, a power range for the RF source ofabout 350 to about 450 Watts, a flow speed for chlorine of about 35 toabout 45 sccm, and a flow speed for hydrogen bromide of about 200 toabout 300 sccm.

[0026] For the first etching step and the second etching step, ifetching duration for the second etching step is about 1 to about 50seconds, then lower electrodes 224 a with wide bases are formed.However, if the etching duration of the second etching step is longer,for example, 80 seconds, then the inclines of lower electrodes 224 abecome more vertical.

[0027] Furthermore, a height difference 214 between doped polysiliconlayer 212 a and dielectric layer 204 is less than a fourth of a heightdifference 216 between lower electrode 224 a and dielectric layer 204.

[0028] Referring to FIG. 2C, after a seeding step and a high vacuumannealing step at about 550 to about 590 degrees Centigrade areperformed, hemi-spherical silicon grains 222 are formed on the surfacesof doped amorphous layer 210 b in lower electrodes 224 a. A gas sourcefor seeding comprises silicane or Si₂H₆ with a preferred flow speed ofless than about 40 sccm.

[0029] Afterwards, a dielectric layer (not shown) and upper electrodes(not shown) are formed on lower electrodes 224 b, and the structures ofthe DRAM capacitors are completed. The processes are not described heresince they are well known to persons familiar with the prior art.

[0030] As embodied and described broadly herein, this invention has atleast the following advantages:

[0031] 1. Hemi-spherical silicon grains can only grow on the surface ofthe doped amorphous silicon layer, and not on the surface of the dopedpolysilicon layer formed before the doped amorphous silicon layer isformed. Therefore, the growth of hemi-spherical silicon grains does notcause bridging between adjacent lower electrodes, nor induces shortcircuits in the capacitors.

[0032] 2. By controlling the flow speeds of the etching gases and theetching duration for the second etching step, wide-based lowerelectrodes are formed to support the narrower tops of lower electrodes,so that the lower electrodes do not fall down.

[0033] It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

What is claimed is:
 1. A method of fabricating a wide-based,box-structured capacitor containing hemi-spherical grains, wherein asubstrate is provided with a source/drain and a first dielectric layeris formed on the substrate with a node contact opening that exposes thesource/drain, the method comprising: forming a doped polysilicon layeron the substrate; forming a doped amorphous silicon layer on the dopedpolysilicon layer; performing a first etching step, wherein a first flowspeed of chlorine and a second flow speed of hydrogen bromide are usedto etch the doped amorphous silicon layer and the doped polysiliconlayer until the first dielectric layer is exposed and a lower electrodeis formed thereon in the node contact opening and on the surroundingfirst dielectric layer; performing a second etching step on the lowerelectrode, wherein a third flow speed of chlorine and a fourth flowspeed of hydrogen bromide are used, and the first flow speed is higherthan the third flow speed and the second flow speed is lower than thefourth flow speed; forming hemi-spherical silicon grains on a surface ofthe doped amorphous silicon layer in the lower electrode; forming asecond dielectric layer on a surface of the lower electrode; and formingan upper electrode on the second dielectric layer.
 2. The method asclaimed in claim 1 , wherein the step of forming the doped polysiliconlayer comprises chemical vapor deposition.
 3. The method as claimed inclaim 1 , wherein the step of forming the doped amorphous silicon layercomprises chemical vapor deposition.
 4. The method as claimed in claim 1, wherein both the first etching step and the second etching stepcomprise anisotropical etching.
 5. The method as claimed in claim 1 ,wherein reaction parameters for the first etching step comprise: apressure range for the reaction chamber of about 12 to about 18militorrs; a power range for a RF source of about 400 to about 500Watts; a flow speed for chlorine of about 60 to about 80 sccm (standardcubic centimeter per minute); and a flow speed for hydrogen bromide ofabout 100 to about 150 sccm.
 6. The method as claimed in claim 1 ,wherein reaction parameters for the second etching step comprise: apressure range for the reaction chamber of about 35 to about 45militorrs; a power range for a RF source of about 350 to about 450Watts; a flow speed for chlorine of about 35 to about 45 sccm; and aflow speed for hydrogen bromide of about 200 to about 300 sccm.
 7. Themethod as claimed in claim 6 , wherein etching duration for the secondetching step is about 1-50 seconds.
 8. The method as claimed in claim 1, wherein a height difference between the doped polysilicon layer andthe first dielectric layer is less than a fourth of a height differencebetween the lower electrode and the first dielectric layer.
 9. Themethod as claimed in claim 1 , wherein the step for forminghemi-spherical silicon grains on the surface of the doped amorphoussilicon layer comprises: seeding the doped amorphous silicon layer; andperforming a high vacuum annealing step.
 10. A method of fabricating awide-based, box-structured capacitor containing hemi-spherical grains,wherein a substrate is provided with a source/drain and a dielectriclayer is formed on the substrate with a node contact opening thatexposes the source/drain, the method comprising: forming a dopedpolysilicon layer on the substrate; forming a doped amorphous siliconlayer on the doped polysilicon layer; performing an etching step,wherein flow speeds of chlorine and of hydrogen bromide are adjusted toetch the doped amorphous silicon layer and the doped polysilicon layerand a wide-based lower electrode is formed thereon in the node contactopening and on the surrounding first dielectric layer; and forminghemi-spherical silicon grains on a surface of the doped amorphoussilicon layer in the lower electrode.
 11. The method as claimed in claim10 , wherein the etching step comprises a first etching step thatincludes flow speeds for chlorine and hydrogen bromide of about 60-80sccm and of about 100-150 sccm, respectively, and a second etching stepthat includes flow speeds for chlorine and hydrogen bromide of about35-45 sccm and of about 200-300 sccm, respectively.
 12. The method asclaimed in claim 10 , wherein the first etching step is performed with areaction chamber pressure of about 12-18 militorrs and a power for a RFsource of about 400-500 Watts, while using the dielectric layer as thestop layer.
 13. The method as claimed in claim 10 , wherein the secondetching step is performed with a reaction chamber pressure of about35-45 militorrs, a power for a RF source of about 350-450 Watts and aduration of about 1-50 seconds.
 14. The method as claimed in claim 10 ,wherein a height difference between the doped polysilicon layer and thedielectric layer is less than a fourth of a height difference betweenthe lower electrode and the dielectric layer.
 15. A structure of awide-based, box-structured capacitor containing hemi-spherical grains,comprising: a substrate containing a source/drain; a first dielectriclayer formed on the substrate with a node contact opening that exposesthe source/drain; a boxed-structured lower electrode containinghemi-spherical silicon grains, sequentially formed by a dopedpolysilicon layer and a doped amorphous silicon layer, wherein the dopedpolysilicon layer fills the node contact opening and has a height higherthan that of the first dielectric layer as well as a width wider thanthat of the doped amorphous silicon layer; a second dielectric layer ona surface of the lower electrode; and an upper electrode on the seconddielectric layer.
 16. The structure as claimed in claim 15 , wherein aheight difference between the doped polysilicon layer and the firstdielectric layer is less than a fourth of a height difference betweenthe lower electrode and the first dielectric layer.